Field effect transistors having multiple stacked channels

ABSTRACT

Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

RELATED APPLICATION

[0001] This application claims the benefit of Korean Patent Application No. 2002-0059886, filed Oct. 1, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.

FIELD OF THE INVENTION

[0002] The present invention relates to integrated circuit devices and methods of manufacturing the same. More particularly, the present invention relates to field effect transistors and methods of manufacturing the same.

BACKGROUND OF THE INVENTION

[0003] Integrated circuit field effect transistors are widely used in logic, memory, processor and other integrated circuit devices. As is well known to those having skill in the art, an integrated circuit field effect transistor includes spaced apart source and drain regions, a channel therebetween and a gate electrode adjacent the channel. Integrated circuit field effect transistors are often referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply as MOS devices. Although these terms will be used in the present application, they are used to generally denote integrated circuit field effect transistors and are not limited to field effect transistors having metal gates or oxide gate insulators.

[0004] As the integration density of integrated circuit field effect transistors continues to increase, the size of the active region and the channel length may continue to decrease. With the reduction in the channel length of the transistor, the influence of the source/drain upon the electric field or potential in the channel region may become considerable. This is called the “short channel effect”. Further, with the scaling down of the active size, the channel width decreases which may increase a threshold voltage. This is called the “narrow width effect”.

[0005] Various structures have been developed in attempts to improve or maximize the device performance, while reducing the sizes of elements formed on a substrate. For example, there are vertical transistor structures known as a fin structure, a DELTA (fully Depleted Lean-channel TrAnsistor) structure and GAA (Gate All Around) structure.

[0006] For example, U.S. Pat. No. 6,413,802 discloses a FinFET device. As noted in the Abstract of this patent, a FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment, two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

[0007] An example of a MOS transistor having DELTA structure is disclosed in U.S. Pat. No. 4,996,574. As noted in the Abstract of this patent, a metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body provided on the insulator layer and comprising a source region, a drain region and a channel region extending in a first direction between and interconnecting the source region and the drain region, a gate insulator film provided on the semiconductor body so as to cover the channel region except for the part of the channel region in contact with the insulator layer, and a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate insulator film except for the part of the channel region in contact with the insulator layer. The channel region has a width substantially smaller than twice the maximum extension of the depletion region formed in the channel region.

[0008] An example of a thin film transistor having the GAA structure is disclosed in U.S. Pat. No. 5,583,362. In typical MOS transistors of GAA structure, the SOI layer serves as an active pattern and a gate electrode is formed surrounding a channel region of the active pattern of which the surface is covered with a gate-insulating layer.

SUMMARY OF THE INVENTION

[0009] Integrated circuit field effect transistor devices according to some embodiments of the present invention include a substrate having a surface and an active channel pattern on the surface. The active channel pattern comprises a plurality of channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel, a respective one of which is between respective adjacent ones of the channels. A gate electrode surrounds the plurality of channels and extends through the at least one tunnel. A pair of source/drain regions also is provided, a respective one of which is on the surface at a respective one of opposite sides of the active channel pattern and is electrically connected to the plurality of channels.

[0010] In some embodiments, the plurality of channels comprises first and second opposite sides and third and fourth opposite sides, wherein a respective one of the source/drain regions are located at a respective one of the first and second opposite sides, and wherein the gate electrode surrounds the plurality of channels on the third and fourth opposite sides and extends through the at least one tunnel. In other embodiments, at least three channels and two tunnels are provided wherein the tunnels extend parallel to the surface to define a series of alternating channels and tunnels that are stacked on the surface in a direction that is orthogonal to the surface. In yet other embodiments, the channels comprise a single crystalline semiconductor film such as silicon. In some embodiments, the source/drain regions have a uniform doping profile in a direction perpendicular to the plurality of channels.

[0011] Integrated circuit field effect transistors are manufactured, according to some embodiments of the present invention, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern comprises a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The plurality of interchannel layers are selectively removed to form a plurality of tunnels passing through the pre-active pattern, to thereby define an active channel pattern comprising the tunnels and a plurality of channels comprising the channel layers. A gate electrode is formed in the tunnels and surrounding the channels.

[0012] In some embodiments, the source/drain regions are formed by etching spaced apart regions of the pre-active pattern and forming source/drain regions in the etched regions. The spaced apart regions may be etched to define first and second opposite sides of the pre-active patterns, and a respective one of the source/drain regions may be formed at a respective one of the first and second opposite sides. The tunnels may pass through the pre-active pattern from third to fourth sides thereof, so that the gate electrode surrounds the channels on the third and fourth sides.

[0013] According to some embodiments of the present invention, multiple thin channels can be formed from one active pattern and the gate electrode surrounds the channels. Since the plurality of thin channels are stacked vertically, areas occupied by the channel region and the source/drain regions may be reduced as compared to, for example, a conventional fin-type MOS transistor.

[0014] Further, in some embodiments, the source/drain regions have a uniform doping profile in a direction perpendicular to the plurality of channels, so that uniform source/drain junction capacitance can be maintained even though the number and area of the channels increase. Thus, while reducing the junction capacitance, the current can be increased to enhance the operating speed of the device.

[0015] Finally, in some embodiments of the present invention, after alternately stacking the plurality of channel layers and the plurality of interchannel layers to form the active pattern, regions of the active pattern where source/drain regions are to be formed are etched away. The etched regions can be provided with an epitaxial single crystalline film or a conductive material to form the source/drain regions. Since the horizontal length of the interchannel layer may be limited within a length region of the gate, it can reduce or prevent the tunnels from extending horizontally when the interchannel layers are isotropically etched to form the tunnels in a subsequent process. Thus, a highly integrated MOS transistor having a gate length smaller than a channel width can be realized in some embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIGS. 1A and 1B are perspective views showing an active pattern and a gate electrode of a MOS transistor having multiple channels in accordance with some embodiments of the present invention, respectively;

[0017]FIG. 2A is a plan view of a device in accordance with first embodiments of the present invention;

[0018]FIGS. 2B and 2C are cross-sectional views of the device of FIG. 2A taken along lines AA′ and BB′ of FIG. 2A, respectively;

[0019]FIGS. 3A to 3R are cross-sectional views illustrating methods of manufacturing a device according to the first embodiments of the present invention;

[0020]FIGS. 4A to 4G are perspective views illustrating some steps of methods of manufacturing a device according to the first embodiments of the present invention;

[0021]FIG. 5 is an enlarged view of a portion “A” in FIG. 3R;

[0022]FIGS. 6A and 6B are a perspective view and a cross-sectional view, respectively, of a device in accordance with second embodiments of the present invention and FIG. 6C is an enlarged view of a portion “B” of FIG. 6B;

[0023]FIGS. 7A to 7M are cross-sectional views illustrating methods of manufacturing a device according to the second embodiments of the present invention;

[0024]FIG. 8 is a cross-sectional view of a device in accordance with third embodiments of the present invention;

[0025]FIGS. 9A to 9J are cross-sectional views illustrating methods of manufacturing a device in accordance with fourth embodiments of the present invention;

[0026]FIG. 10 is a cross-sectional view of a device according to fifth embodiments of the present invention;

[0027]FIG. 11 is a cross-sectional view of a device according to sixth embodiments of the present invention;

[0028]FIG. 12 is a cross-sectional view of a device in accordance with seventh embodiments of the present invention;

[0029]FIG. 13 is a cross-sectional view of a device in accordance with eighth embodiments of the present invention;

[0030]FIG. 14 is a cross-sectional view of a device according to ninth embodiments of the present invention;

[0031]FIGS. 15A to 15F are cross-sectional views illustrating methods of manufacturing a device according to tenth embodiments of the present invention; and

[0032]FIGS. 16A to 16C are cross-sectional views illustrating methods of manufacturing a device in accordance with eleventh embodiments of the present invention.

DETAILED DESCRIPTION

[0033] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Moreover, each embodiment described and illustrated herein includes its complementary conductivity type embodiment as well. Like numbers refer to like elements throughout.

[0034] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. It will be understood that if part of an element, such as a surface of a conductive line, is referred to as “outer,” it is closer to the outside of the substrate than other parts of the element. Furthermore, relative terms such as “beneath” may be used herein to describe a relationship of one layer or region to another layer or region relative to a substrate or base layer as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. Finally, the term “directly” means that there are no intervening elements.

[0035]FIGS. 1A and 1B are perspective views showing an active pattern and a gate electrode of a MOS transistor having multiple channels, respectively, in accordance with some embodiments of the present invention.

[0036] Referring to FIG. 1A, an active pattern formed on a surface of an integrated circuit substrate such as a semiconductor substrate (not shown) includes a plurality of channels 4 a, 4 b and 4 c formed in a vertical direction. Though three channels 4 a, 4 b and 4 c are shown in the embodiment, two channels may be formed or the number of channels may be more than three.

[0037] The channels 4 a, 4 b and 4 c have a vertically stacked structure with a narrow width. A plurality of tunnels 2 a, 2 b and 2 c are formed between the channels 4 a, 4 b and 4 c. Source/drain regions 3 are formed at the both sides of the active pattern so as to be connected to the plurality of channels 4 a, 4 b and 4 c.

[0038] The source/drain regions 3 are formed to have a width wider than that of the channels 4 a, 4 b and 4 c. Between the source/drain regions 3 and the channels 4 a, 4 b, 4 c, there may be formed source/drain extension layers 5 connecting the source/drain regions 4 to the channels 4 a, 4 b and 4 c.

[0039] Particularly, the active pattern comprises the source/drain regions 3 of a rectangular parallelepiped shape having a relatively wide width on the both sides of the active pattern. It will be understood, however, that the active pattern may have any polygonal shape, and that the sides and vertices need not be equal. A channel region having a width narrower than the rectangular parallelepiped shape is formed between the source/drain regions 3 to connect the source/drain regions 3 to each other. The channel region includes two source/drain extension layers 5 connected to the source/drain regions 3. Two source/drain extension layers 5 are connected to each other by the plurality of channels 4 a, 4 b and 4 c formed in a vertical direction. The plurality of tunnels 2 a, 2 b and 2 c are formed between the channels 4 a, 4 b and 4 c. The lowest tunnel 2 a is formed between the lowest channel layer 4 a and the underlying surface portion of the semiconductor substrate. A groove 2′ of a tunnel shape is formed on the uppermost channel 4 c.

[0040] Referring to FIG. 1B, a gate electrode 6 is formed on the active pattern. While extending through and/or filling up the plurality of tunnels 2 a, 2 b and 2 c and the tunnel groove 2′, the gate electrode 6 is formed to surround the plurality of channels 4 a, 4 b and 4 c in a vertical direction (i.e., a direction perpendicular to the forming direction of the source/drain regions on the plan). A gate-insulating layer 7 is formed between the gate electrode 6 and the plurality of channels 4 a, 4 b and 4 c.

[0041] The semiconductor substrate comprises silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI) and/or other conventional substrates. In some embodiments, the semiconductor substrate comprises a single crystalline Si.

[0042] The channels 4 a, 4 b and 4 c comprise a single crystalline semiconductor film, such as silicon film. The source/drain regions 3 comprise a selective epitaxial single crystalline film or a conductive film such as a polysilicon film, a metal film, a metal silicide film, etc. In case of using the selective epitaxial single crystalline film or the polysilicon film, an impurity is ion-implanted in the source/drain regions 3 so that the source/drain regions 3 are conductive.

[0043] In case of forming the source/drain extension layers 5 between the channels 4 a, 4 b and 4 c and the source/drain regions 3 as shown in the figure, in some embodiments the source/drain regions 3 comprise a conductive film such as a polysilicon film, a metal film, a metal silicide film, etc. and the source/drain extension layer 3 comprises a selective epitaxial single crystalline film.

[0044] The gate electrode 6 comprises a polysilicon film and may include a gate stack layer 8 formed on the top surface of the gate electrode 6. The gate stack layer 8 comprises a metal silicide for reducing a gate resistance and/or an insulating material for capping the gate electrode 6. The gate-insulating layer 7 comprises a thermal oxide film or an ONO film.

[0045] In a MOS transistor of some embodiments of the present invention, the plurality of thin channels 4 a, 4 b and 4 c are connected to the source/drain regions 3 and the source/drain regions 3 are formed to have a uniform doping profile in a direction perpendicular to the plurality of channels 4 a, 4 b and 4 c, which can maintain the uniform source/drain junction capacitance even though the number of the channels increases. So, while reducing or minimizing the junction capacitance, the current can increase to enhance the device speed.

[0046] Further, the MOS transistor having a gate electrode smaller than a channel width may be provided in some embodiments because the gate electrode 6 surrounds the plurality of channels 4 a, 4 b and 4 c, which can result in an improvement in the device integration.

[0047] In addition, in some embodiments, regions of the active pattern where source/drain regions are to be formed are etched away, in which the active pattern comprises a plurality of interchannel layers serving as the tunnel 2 and a plurality of channel layers serving as the channels 4 a, 4 b and 4 c which are stacked alternately with each other. Then, the etched regions are provided with and/or filled up with an epitaxial single crystalline film and/or a conductive material to form the source/drain regions 3. Accordingly, only active pattern of the channel region may remain, so that a horizontal length of the tunnel 2 filled with the gate electrode may be limited within a gate length region to thereby obtain a highly integrated MOS transistor having a smaller gate length than a channel width.

Embodiment 1

[0048]FIG. 2A is a plan view of a semiconductor device in accordance with first embodiments of the present invention. FIGS. 2B and 2C are cross-sectional views of the semiconductor device taken along lines AA′ and BB′ of FIG. 2A, respectively.

[0049] Referring to FIGS. 2A to 2C, an active pattern 30 including multiple channels 44 having a plurality of channels 44 a and 44 b formed vertically in the upside direction is formed on a main surface of a substrate 10 comprising silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI) and/or other conventional materials/layers. Source/drain regions 34 are formed so as to be connected to the channels 44 a and 44 b at opposite sides of the active pattern 30. Between the source/drain regions 34 and the plurality of channels 44 a and 44 b, there are formed source/drain extension layers 32 connected to the source/drain regions 34 and connected to the channels 44 and 44 b. That is, the source/drain extension layers 32 serve as a bridge linking the source/drain regions 34 to the plurality of channels 44 a and 44 b.

[0050] A plurality of tunnels 42 is formed between the plurality of channels 44 a and 44 b. The lowest tunnel 42 a is formed between the lowest channel layer 44 a and the underlying surface portion of the semiconductor substrate, i.e., a heavily doped impurity region 12 of the substrate 10. A groove 42 c of a tunnel shape is formed on the uppermost channel 44 b.

[0051] The channels 44 a and 44 b may comprise a semiconductor material such as single crystalline Si, while the source/drain regions 34 may comprise a conductive material such as polysilicon, metal, metal silicide, etc. Here, the source/drain extension layers 32 are formed to be extended from the channels 44 a and 44 b using the same material as in the channels 44 a and 44 b. In some embodiments, the source/drain extension layers 32 are comprised of selective epitaxial single crystalline Si.

[0052] On the active pattern 30, there is formed a gate electrode 48 extending through and/or filling up the tunnel 42 including the plurality of tunnels 42 a and 42 b formed between the channels 44 a and 44 b and surrounding the channels 44 a and 44 b in a vertical direction. A gate-insulating layer 46 is formed between the gate electrode 48 and the channels 44 a and 44 b, i.e., on the inner surfaces of the tunnel 42 and on the inner sidewalls and bottom surfaces of the groove 42 of a tunnel shape. In some embodiments, the gate electrode 48 comprises a polysilicon and a gate stack layer 50 of a metal silicide for reducing a gate resistance is formed on the top surface of the gate electrode 48.

[0053] Field regions 22 are formed so as to surround the source/drain regions 34 except the channel region of the plurality of channels 44 a and 44 b. A heavily doped region 12 is formed in the main surface portion of the substrate 10 below the active pattern 30, i.e., below the lowest channel 44 a. The heavily doped region 12 can reduce or prevent the operation of a bottom transistor causing a short channel effect.

[0054]FIGS. 3A to 3R are cross-sectional views illustrating methods of manufacturing a semiconductor device according to the first embodiments of the present invention. FIGS. 4A to 4G are perspective views illustrating some steps of the methods of manufacturing a semiconductor device according to the first embodiments of the present invention.

[0055] Referring to FIG. 3A, an impurity of the same conductivity type as that of a substrate 10 is ion-implanted into a main surface of the substrate 10 to form a heavily doped region (well region) 12 which can reduce or prevent the operation of a bottom transistor. The substrate 10 comprises silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI) and/or other conventional substrates/layers. In some embodiments, the semiconductor substrate 10 comprises single crystalline Si.

[0056] Referring to FIG. 3B, a plurality of interchannel layers 14 and a plurality of channel layers 16 are stacked alternately upon each other on the substrate 10. First, a first interchannel layer 14 a is formed on the substrate 10, and then, a first channel layer 16 a is formed on the first interchannel layer 14 a. An uppermost interchannel layer 16 c is formed at an uppermost position.

[0057] The channel layers 16 and the interchannel layers 14 are comprised of single crystalline semiconductor materials having an etch selectivity with respect to each other. In some embodiments, the channel layers 16 are formed from a single crystalline Si epitaxial film having a thickness of about 300 Å and the interchannel layers 14 are formed from a single crystalline Ge or a single crystalline SiGe epitaxial film having a thickness of about 300 Å.

[0058] The repeating number and thickness of the channel layers 16 and the interchannel layers 14 can be controlled in accordance with a purpose of a transistor to be formed. In some embodiments, the channel layers 16 and the interchannel layers 14 are stacked alternately with each other such that the total thickness becomes about 100˜1500 Å. Here, in order to perform a channel doping, the channel layers 16 may be formed of a doped single crystalline Si epitaxial film.

[0059] Referring to FIG. 3C, the plurality of channel layers 16 and the plurality of interchannel layers 14 are patterned through a photolithography process to form a pre-active pattern 18 having a first channel layer pre-pattern (or first channel layer preliminary pattern) 16′ and a first interchannel layer pre-pattern (or first interchannel layer preliminary pattern) 14′. The first channel layer pre-pattern 16′ comprises a plurality of first channel layer patterns 16 a′ and 16 b′. The first interchannel layer pre-pattern 14′ comprises a plurality of interchannel layer patterns 14 a′, 14 b′ and 14 c′. The etching process is performed for sufficient time to form an isolation trench 20 having a depth deeper than that of the impurity region 12 in the substrate 10.

[0060] Next, an oxide layer is deposited by a chemical vapor deposition (CVD) method so as to fill up the isolation trench 20. The deposited oxide layer is planarized by an etch-back process or a chemical mechanical polishing (CMP) process until the surface of the pre-active pattern 18 is exposed, thereby forming field regions 22 surrounding the pre-active pattern 18.

[0061] Referring to FIG. 3D, an etch-stopping layer 23, a dummy gate layer 25 and an anti-reflective layer 27 are successively stacked on the substrate 10 including the pre-active pattern 18. The etch-stopping layer 23 is formed to a thickness of about 100˜200 Å by a material having an etch selectivity with respect to the dummy gate layer 25, such as silicon nitride. The etch-stopping layer 23 plays a role of reducing or preventing the underlying pre-active pattern from being etched during etching the dummy gate layer 25. The dummy gate layer 25 for defining a gate region is formed to a thickness of about 1000 Å by silicon oxide. The anti-reflective layer 27 for reducing or preventing the reflection of light from the lower substrate during a photolithography process is formed to a thickness of about 300 Å by using silicon nitride.

[0062] Referring to FIG. 3E, through a photolithography process, the anti-reflective layer 27, the dummy gate layer 25 and the etch-stopping layer 23 are successively dry-etched away to form a gate hard mask 29 having an anti-reflective layer pattern 28, a dummy gate pattern 26 and an etch-stopping layer pattern 24. The gate hard mask 29 has a width of about 0.2˜0.3 μm and plays a role of self-aligning the source/drain regions to the channel region.

[0063] Referring to FIG. 3F, using the gate hard mask 29 as an etching mask, the exposed pre-active pattern 18 is etched away until the surface of the substrate 10 is exposed, thereby defining regions 30 where the source/drain regions are to be formed. Thus, only the channel region of the pre-active pattern 18 remains. At this time, the etching process is preformed for sufficient time to etch the upper portion of the semiconductor substrate 10 to below the projected range of the heavily doped region 12.

[0064] As a result, there are formed an active channel pattern 18 a including a second channel layer pattern 16″ and a second interchannel layer pattern 14″ under the gate hard mask 29 as shown in the figure. The second channel layer pattern 16″ is comprised of a plurality of second channel layer patterns 16 a″ and 16 b″ and the second interchannel layer pattern 14″ is comprised of a plurality of interchannel layer patterns 14 a″, 14 b″ and 14 b″.

[0065] In a conventional GAA structure where the active region is not etched and utilized as the source/drain regions, the tunnel may extend horizontally to increase the length of the gate electrode when isotropically etching the interchannel layer. In contrast, in some embodiments of the present invention, the regions of the active pattern where the source/drain regions are to be formed are etched and then, the etched regions are filled up with a conductive material to form the source/drain. Accordingly, since the horizontal length of the interchannel layers 14 constituting the active channel pattern 18 a can be limited within the gate length region, it can reduce or prevent tunnels from extending horizontally when the second interchannel layers 14″ are isotropically etched to form the tunnels in a subsequent process. So, a highly integrated MOS transistor having a gate length smaller than a channel width can be obtained.

[0066] Referring to FIG. 3G, a selective epitaxial single crystalline film is partially grown to a thickness of about 300˜400 Å on the surfaces of the etched regions 30 of the semiconductor substrate 10 and on the side of the active channel pattern 18 a, thereby forming source/drain extension layers 32. Here, the selective epitaxial single crystalline film is doped by a tilted ion implantation so that each of the second channel layer patterns 16 a″ and 16 b″ have a uniform source/drain impurity concentration. In some cases, with or without performing the ion implantation, a dopant is solid-phase diffused from source/drain regions that are heavily doped in a subsequent annealing process to thereby form the source/drain extension layers 32 having a uniform source/drain doping concentration with respect to each of the channel layers 16.

[0067] Referring to FIG. 3H, a conductive material is deposited on the source/drain extension layers 32, and in some embodiments so as to completely fill up the etched regions 30, thereby forming a conductive film. Then, the conductive film is etched back to the surface of the active channel pattern 18 a to form the source/drain regions 34 comprising the heavily doped conductive film only within the etched regions 30.

[0068] In some embodiments, the conductive material comprises doped polysilicon, metal and/or metal silicide. As described above, in some embodiments, the source/drain regions 34 have a uniform doping profile vertically along the active channel pattern 18 a because the source/drain regions 34 are formed by deposition. Here, tails 34 a of the conductive film for the source/drain may remain under the side of the gate hard mask 29.

[0069] Optionally, in order to reduce the surface roughness of the source/drain extension layers 32 comprising the epitaxial single crystalline film and to recrystallize the source/drain extension layers 32, a heat treatment may be performed at a high temperature in a hydrogen (H₂) ambient before depositing the conductive film.

[0070] Referring to FIG. 3I, silicon nitride is deposited so as to cover the gate hard mask 29 on the source/drain regions 34 and the field regions 22, thereby forming a mask layer 35. Preferably, the mask layer 35 comprises the same material as that of the uppermost layer constituting the gate hard mask 29, i.e., the anti-reflective layer pattern 28. Here, before depositing the mask layer 35, an oxide layer may be formed by oxidizing the surface portions of the source/drain regions 34 and the exposed surface portion of the active channel pattern 18 a of the channel region through a thermal oxidation process. This oxide layer serves as a stress-buffering layer.

[0071] Referring to FIG. 3J, until the surface of the dummy gate pattern 26 is exposed, the mask layer 35 is removed by etch-back or chemical mechanical polishing to form mask patterns 36 exposing the dummy gate pattern 26. FIG. 4A is a perspective side view particularly illustrating the step as shown in FIG. 3J.

[0072] Referring to FIG. 3K, using the mask patterns 26, the dummy gate pattern 26 is selectively removed to form a gate trench 38. The etch-stopping layer pattern 24 reduces or prevents the underlying pre-active pattern 18 from being etched during the etching process of removing the dummy gate pattern 26. FIG. 4B is a perspective side view particularly illustrating the step as shown in FIG. 3K.

[0073] Referring to FIG. 3L, if the conductive tails 34 a remain under the sides of the gate hard mask 29, an oxidation process and/or a wet etching process is executed to remove the conductive tails 34 a. In some embodiments, the oxidation process is carried out to convert the conductive tails 34 a into the insulating layers 40, thereby preventing the conductive tails 34 a from being short-circuited with a gate electrode to be formed in a subsequent process.

[0074] Referring to FIG. 3M, the etch-stopping layer pattern 24 exposed through the gate trench 38 is removed.

[0075] When the active channel pattern 18 a of the channel region is not doped with impurities, a channel ion implantation is locally performed through the gate trench 38 to thereby dope the active channel pattern 18 a of the channel region with impurities. In some embodiments, the channel ion implantation is carried out such that the projected range is formed within each of the second channel layer patterns 16 a″ and 16 b″. Here, the reference numeral 41 indicates the channel ion-implanted regions. Further, in some embodiments, the channel ion implantation is executed such that each of the second channel layer patterns 16 a″ and 16 b″ may have different doping concentrations from each other, thereby obtaining a transistor that may be operated according to the applied gate voltage.

[0076] Next, using the source/drain regions 34 as an etching mask, the field regions 22 are selectively etched away to expose the sides of the active channel pattern 18 a of the channel region, as shown in FIG. 4C. FIG. 4C is a perspective side view particularly showing a portion that is not shown in the cross-sectional view of FIG. 3M.

[0077] Referring to FIG. 3N, through an isotropic etching process, the plurality of interchannel layer patterns 14 a″, 14 b″ and 14 c″ are selectively removed to form a plurality of tunnels 42 a and 42 b passing through the active channel pattern 18 a and a tunnel groove 42 c in a tunnel shape, the tunnel groove 42 c being located at an uppermost position. Here, the second channel layer patterns 16 a″ and 16 b″ form a plurality of channels 44 a and 44 b. Preferably, the plurality of tunnels 42 a and 42 b and the plurality of channels 44 a and 44 b are formed to have the same width as that of the dummy gate pattern 26 within a range of about 50%.

[0078]FIG. 4D is a perspective side view particularly illustrating the step as shown in FIG. 3N. As shown, the side surface portions of the source/drain extension layers 32 are partially exposed through the tunnels 42 a and 42 b.

[0079] Referring to FIG. 3O, a thermal oxidation process is carried out to form a gate-insulating layer 46 to a thickness of about 10˜70 Å on the surfaces of the plurality of channels 44 a and 44 b and the inner surface of the tunnel groove 42 c. FIG. 4E is a perspective side view particularly illustrating the step as shown in FIG. 3O. As shown in the figure, the gate-insulating layer 46 is also continuously formed on a portion of the surfaces of the source/drain extension layers 32 exposed by the channels.

[0080] Here, in order to reduce the surface roughness of the channels 44 a and 44 b, a heat treatment may be performed at a high temperature in a hydrogen (H₂) or argon (Ar) ambient before forming the gate-insulating layer 46, thereby decreasing the roughness between the gate-insulating layer 46 and the channels. Alternatively, the gate-insulating layer 46 may be comprised of silicon oxynitride.

[0081] Referring to FIG. 3P, a gate electrode 48 is formed so as to fill up the plurality of tunnels 42 a and 42 b and the tunnel groove 42 c and to surround the plurality of channels 44 a and 44 b. In some embodiments, the gate electrode 48 comprises doped polysilicon. FIG. 4F is a perspective side view particularly showing the step as shown in FIG. 3P.

[0082] Referring to FIG. 3Q, a gate stack layer 50 including a metal silicide for reducing a gate resistance is formed on the polysilicon gate electrode 48. Here, the gate stack layer 50 may be comprised of an insulating material for capping the gate, e.g., silicon oxide or silicon nitride. FIG. 4G is a perspective side view illustrating the step as shown in FIG. 3Q.

[0083] Referring to FIG. 3R, the mask patterns 36 are removed and then, subsequent processes such as metal interconnection are carried out to complete a vertical MOS transistor having multiple channels. In some cases, the mask patterns 36 may remain to serve as an insulating interlayer.

Embodiment 2

[0084]FIG. 5 is an enlarged view showing a portion “A” in FIG. 3R. Referring to FIG. 5, in the vertical MOS transistor in Embodiment 1, the gate-insulating layer 46 exists between the gate electrode 48 and the source/drain regions 34 (specifically, source/drain extension layers 32) to thereby cause an overlap capacitance between the gate electrode 48 and the source/drain regions 34 as shown by a capacitor symbol (

). A vertical MOS transistor of the present embodiments is presented to reduce or suppress the generation of the above overlap capacitance.

[0085]FIG. 6A is a perspective view of a semiconductor device in accordance with the present embodiment and FIG. 6B is a cross-sectional view taken along line C-C′ of FIG. 6A. In the present embodiment, gate spacers 54 comprising an insulating material are formed between the gate electrode 48 and the source/drain regions 34 so as to reduce or prevent an increase in the overlap capacitance (see FIG. 5) between the gate electrode 48 and the source/drain regions 34. In the present embodiment, the same elements as those in Embodiment 1 are indicated by the same numerals.

[0086] Referring to FIGS. 6A and 6B, an active pattern 30 including a plurality of channels 44 a and 44 b formed vertically in the upward direction are formed on a main surface of a substrate 10 comprised of silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI) and/or other conventional substrates/layers. Source/drain regions 34 are connected with the plurality of channels 44 a and 44 b on both sides of the active pattern 30. Between the source/drain regions 34 and the plurality of channels 44 a and 44 b, there are formed source/drain extension layers 32 connected to the source/drain regions 34 and connected to the channels 44 and 44 b.

[0087] Between each of the channels 44 a and 44 b, there are formed a plurality of tunnels 42 having a length shorter than the channel length. The lowest tunnel 42 a is formed between the lowest channel layer 44 a and the underlying surface portion of the substrate, i.e., an impurity-doped region 12. A tunnel groove 42 c having a tunnel shape is formed on the uppermost channel 44 b.

[0088]FIG. 6C is an enlarged view showing a portion “B” in FIG. 6B. Upon both sidewalls of the tunnel 42 and both sidewalls of the tunnel groove 42, two gate spacers 54 of an insulating layer are formed so that each of the gate spacers has a thickness (d) corresponding half the difference between the length of the channels 44 a and 44 b and the length of the tunnel 42 as shown in FIG. 6C. Over the active pattern 30, there is formed a gate electrode 48 extending through and/or filling up the plurality of tunnels 42 a and 42 b and the tunnel groove 42 c and surrounding the plurality of channels 44 a and 44 b. A gate-insulating layer 46 is formed between the gate electrode 48 and the plurality of channels 44 a and 44 b, i.e., on the upper surface and the lower surface of the tunnel 42 and the lower surface of the tunnel groove 42 c except for the sidewalls of the tunnel and the sidewalls of the tunnel groove. 30

[0089] In some embodiments, the gate electrode 48 comprises a polysilicon and a gate stack layer 50 composed of a metal silicide and is formed on the top surface of the gate electrode 48. The gate stack layer 50 is formed to surround the upper portion of the sidewalls of the gate electrode 48, thereby making the notched gate electrode. Field regions 22 are formed so as to surround the source/drain regions 34 except the channel region including the plurality of channels 44 a and 44 b.

[0090] Heavily doped region 12 is formed in the main surface portion of the substrate 10 below the active pattern 30 so as to reduce or prevent the operation of a bottom transistor.

[0091]FIGS. 7A to 7M are cross-sectional views illustrating methods of manufacturing a semiconductor device according to the second embodiments of the present invention. Referring to FIG. 7A, in the same manner as shown in FIGS. 3A to 3F of Embodiment 1, a pre-active pattern 18, in which a plurality of interchannel layers 14 and a plurality of channel layers 16 are stacked alternately with each other, and field regions 22 surrounding the pre-active pattern 18 are formed on a substrate 10. In some embodiments, the interchannel layers 14 comprise single crystalline Ge or single crystalline SiGe film, while the plurality of channel layers 16 comprise single crystalline Si film.

[0092] Next, a gate hard mask for self-aligning source/drain regions to the channel region is formed on the pre-active pattern 18. The gate hard mask has an etch-stopping layer pattern 24, a dummy gate pattern 26 and an anti-reflective layer pattern 28 which are successively stacked.

[0093] Using the gate hard mask, the pre-active pattern 18 is etched away until the surface of the substrate 10 is exposed, thereby defining regions 30 where the source/drain regions are to be formed. By doing so, only the channel region of the pre-active pattern 18 remains. The etching process is further preformed for sufficient time to etch the upper portion of the semiconductor substrate 10 to below the projected range of the heavily doped region 12.

[0094] As a result, an active channel pattern 18 a having a second channel layer pattern 16″ and a second interchannel layer pattern 14″ is formed under the gate hard mask 29 as shown in the figure. The second channel layer pattern 16″ is comprised of a plurality of second channel layer patterns 16 a″ and 16 b″ and the second interchannel layer pattern 14″ is comprised of a plurality of interchannel layer patterns 14 a″, 14 b″ and 14 c″.

[0095] Referring to FIG. 7B, the second interchannel layer patterns 14″ are selectively lateral-etched through the exposed sides of the active channel pattern 18 a, thereby forming undercut regions 31. A width of the undercut region 31 is formed to a depth of about 500˜700 Å from the sidewall surface of the original active channel pattern 18 a. Accordingly, a plurality of third interchannel layer patterns 15 a, 15 b and 15 c shorter than the length of the second channel layer patterns 16 a″ and 16 b″ are formed from the plurality of second interchannel layer patterns 14 a″, 14 b″ and 14 c″.

[0096] Referring to FIG. 7C, an insulating layer 52 is deposited so as to be formed in or fill up the undercut regions 31 on the entire surface of the resultant structure. Particularly, an insulating material such as silicon oxide is deposited so as to fill up the undercut regions 31 of the active channel pattern 18 a through a chemical vapor deposition method, thereby forming the insulating layer 52 covering the entire surface of the resultant structure, i.e., the entire inner surface of the etched regions 30 including the sidewalls and the surface of the active channel pattern 18 a.

[0097] Referring to FIG. 7D, the insulating layer 52 is etched back to form gate spacers 54 comprised of an insulating material such silicon oxide filling up only the undercut regions 31.

[0098] Referring to FIG. 7E, in the same manner as shown in FIG. 3G of Embodiment 1, a selective epitaxial single crystalline film is partially grown on the surfaces of the etched regions 30 and the sides of the active channel pattern 18 a, thereby forming source/drain extension layers 32.

[0099] Then, in the same manner as shown in FIG. 3H of Embodiment 1, a conductive film such as doped polysilicon, metal or metal silicide is deposited on the entire surface of the resultant structure including the source/drain extension layers 32 and then, the conductive film is etched back to form source/drain regions 34 filling up the etched regions 30.

[0100] Here, before depositing the conductive film, a tilted ion implantation may be executed to dope the source/drain extension layers 32 of the selective epitaxial single crystalline film with impurities. Alternatively or in addition, the source/drain extension layers 32 can be doped by solid-phase diffusing a dopant from the source/drain regions in a subsequent annealing process. In either case, the source/drain extension layers 32 and the source/drain regions 34 can have a uniform doping profile in a direction perpendicular to the channel region.

[0101] Referring to FIG. 7F, in the same manner as shown in FIG. 3I of Embodiment 1, silicon nitride is deposited on the source/drain regions 34, the active channel pattern 18 a of the channel region and the substrate 10, thereby forming a mask layer. Then, in the same manner as in FIG. 3J of Embodiment 1, the mask layer is planarized until the surface of the dummy gate pattern 26 is exposed, thereby forming a mask pattern 36 exposing the dummy gate pattern 26.

[0102] Referring to FIG. 7G, in the same manner as shown in FIG. 3K of Embodiment 1, the dummy gate pattern 26 is selectively removed by using the mask pattern 36, thereby forming a gate trench 38. Here, the etch-stopping layer pattern 24 prevents the underlying active channel pattern 18 a from being etched during the etching process of removing the dummy gate pattern 26. If conductive tails 34 a for source/drain remain under the sides of the gate pattern 26, an oxidation process may be carried out to convert the conductive tails 34 a into insulating layers 40 of silicon oxide in the same manner as in FIG. 3L of Embodiment 1.

[0103] Referring to FIG. 7H, the etch-stopping layer pattern 24 exposed through the gate trench 38 is removed in the same manner as shown in FIG. 3M of Embodiment 1. If the active channel pattern 18 a of the channel region is not doped, an impurity is locally ion-implanted through the gate trench 38 to thereby dope the active channel pattern 18 a of the channel region with impurities. In some embodiments, the channel ion implantation is carried out such that the projected range is formed within each of the channel layers 16″. Alternatively, in other embodiments, the channel ion implantation is executed such that each of the second channel layer patterns 16 a″ and 16 b″ has a different doping concentration from each other, thereby successively operating the transistors according to the applied gate voltage.

[0104] Silicon oxide is deposited on the entire surface of the resultant structure by a chemical vapor deposition method, thereby forming an insulating layer with the same thickness equal to or somewhat larger than the width of the width of the undercut region 31, e.g., about 500˜700 Å thick. Then, the insulating layer is etched back to form insulating layer spacers 56 on the inner sidewalls of the gate trench 38. The insulating layer spacers 56 control the channel width and the gate width.

[0105] Referring to FIG. 7I, in the same manner as shown in FIG. 3N of Embodiment 1, the field regions 22 are selectively etched using the source/drain regions 34 as an etching mask, thereby exposing the sides of the active channel pattern 18 a of the channel region. Then, the plurality of third interchannel layer patterns 15 a, 15 b and 15 c are selectively removed through an isotropic etching process, thereby forming a plurality of tunnels 42 a and 42 b passing through the active channel pattern 18 a and a tunnel groove 42 c located at an uppermost position. Here, the second channel layer patterns 16 a″ and 16 b″ form a plurality of channels 44 a and 44 b. The tunnels 42 a and 42 b are formed to have a length shorter than the horizontal length of the channels 44 a and 44 b due to the gate spacers 54 formed on the sidewalls thereof.

[0106] Referring to FIG. 7J, in the same manner as shown in FIG. 3O of Embodiment 1, a thermal oxidation process is carried out to form a gate-insulating layer 46 on the surface portions of the plurality of channels 44 a and 44 b (particularly, the upper surface and the lower surface of the plurality of tunnels 42 a and 42 b and the bottom surface of the tunnel groove 42 c). Here, in order to reduce the surface roughness of the channels 44 a and 44 b, a heat treatment may be performed at a high temperature in a hydrogen (H₂) or argon (Ar) ambient before forming the gate-insulating layer 46.

[0107] Referring to FIG. 7K, in the same manner as shown in FIG. 3P of Embodiment 1, a gate electrode 48 is formed so as to fill up the tunnels 42 a and 42 b and the tunnel groove 42 c and to surround the channels 44 a and 44 b. In some embodiments, the gate electrode 48 comprises a doped polysilicon.

[0108] Referring to FIG. 7L, the insulating layer spacers 56 are selectively removed to expose the top surface and a portion of the sidewalls of the gate electrode 48. That is, spacer residues 56 a remain on the lower portion of the sidewalls of the gate electrode 48.

[0109] Referring to FIG. 7M, in the same manner as shown in FIG. 3G of Embodiment 1, a gate stack layer 50 having a metal silicide for reducing a gate resistance is formed on the top surface and a portion of the upper sidewalls of the exposed gate electrode 48. Here, the width of the gate stack layer 50 is same as the length of the channels 44 a and 44 b, while the width of the gate electrode 48 is same as the length of the tunnel 42. Accordingly, there is formed a notched gate profile where the gate stack layer 50 protrudes as compared with the gate electrode 48. The notched gate profile can reduce the contact resistance between the gate electrode 48 and the gate stack layer 50.

[0110] Next, the insulating layer spacers 56 and the mask patterns 36 are removed as shown in FIG. 6B.

[0111] According to the second embodiments of the present invention, the gate spacers 54 comprised of an insulating material are formed between the gate electrode 48 and the source/drain regions 34, which can decrease the overlap capacitance between the gate electrode and the source/drain. Further, the contact resistance between the gate electrode 48 and the gate stack layer 50 can be reduced because the gate stack layer 50 is formed to surround a portion of the sidewalls of the gate electrode 48.

Embodiment 3

[0112]FIG. 8 is a cross-sectional view of a device in accordance with third embodiments of the present invention. A device of the present embodiments is similar to the device of Embodiment 2 except that the polysilicon gate electrode 48 has the same width as that of the gate stack layer 50 a comprised of a metal silicide.

[0113] A gate-insulating layer 46 is formed in the same manner as shown in FIGS. 7A to 7J of Embodiment 2. Thereafter, a polysilicon gate electrode 48 is formed so as to extend through and/or fill the plurality of tunnels 42 a and 42 b and the tunnel groove 42 c and to surround the plurality of channels 44 a and 44 b. Accordingly, the polysilicon gate electrode 48 is formed to have the same width as the horizontal width of the tunnels 42 a and 42 b.

[0114] After forming the gate stack layer 50 comprising a metal silicide on the polysilicon gate electrode 48, the insulating layer spacers 56 formed on the sidewalls of the gate trench 38 are removed. So, the gate stack layer 50 is formed to have the same width as that of the gate electrode 48.

[0115] In the same manner as in Embodiment 1, a conductive material is deposited and etched back to form source/drain regions 34, after growing an epitaxial single crystalline film on the sides of the active channel pattern of the channel region to form source/drain extension layers. Alternatively, the etched regions of the active pattern is provided with or filled with an epitaxial single crystalline film or a conductive material such as doped polysilicon, metal, metal silicide, etc., to thereby form the source/drain regions 34 as shown in FIG. 8.

Embodiment 4

[0116]FIGS. 9A to 9J are cross-sectional views illustrating methods of manufacturing semiconductor devices in accordance with fourth embodiments of the present invention. In the present embodiments, the same elements as those in Embodiment 1 are indicated by the same numerals.

[0117] Referring to FIG. 9A, in the same manner as shown in FIGS. 3A to 3F of Embodiment 1, an pre-active pattern 18 in which a plurality of interchannel layers 14 and a plurality of channel layers 16 are stacked alternately with each other and field regions 22 surrounding the pre-active pattern 18 are formed on a semiconductor substrate 10. In some embodiments, the interchannel layers 14 comprise single crystalline Ge film or single crystalline SiGe film, while the channel layers 16 comprise single crystalline Si film.

[0118] Next, a gate hard mask 29 comprising an etch-stopping layer pattern 24, a dummy gate pattern 26 and an anti-reflective layer pattern 28 is formed on the pre-active pattern 18.

[0119] Using the gate hard mask 29, the pre-active pattern 18 is etched away until the surface of the substrate 10 is exposed, thereby forming regions 30 where the source/drain regions are to be formed. Thus, on the channel region under the gate hard mask 29, an active channel pattern 18 a comprising a second channel layer pattern 16″ and a second interchannel layer pattern 14″ is formed from the pre-active pattern 18 as shown. The second channel layer pattern 16″ is comprised of a plurality of second channel layer patterns 16 a″ and 16 b″ and the second interchannel layer pattern 14″ is comprised of a plurality of interchannel layer patterns 14 a″, 14 b″ and 14 c″. The etching process is further preformed for sufficient time to etch the upper portion of the substrate 10 to below the projected range of the heavily doped region 12.

[0120] Thereafter, an oxidation blocking layer 58 comprising a material having an etch selectivity with respect to the field regions 22, such as silicon nitride, is formed on the inner surfaces of the etched regions 30, the surface of the active channel pattern 18 a and the surfaces of the field regions 22.

[0121] Referring to FIG. 9B, the oxidation blocking layer 58 is anisotropically etched away to form anti-oxidation spacers 58 a only the sidewalls of the active channel pattern 18 a and the inner sides of the etched regions 30 and simultaneously, to expose the surface 59 of the semiconductor substrate 10 of the etched regions 30, i.e., the bottoms of the source/drain.

[0122] Referring to FIG. 9C, through a thermal oxidation process, the exposed surface of the substrate 59 is oxidized to form insulating layer patterns 60 comprised of silicon oxide only on the bottoms of the source/drain. Referring to FIG. 9D, the anti-oxidation spacers 58 a are selectively removed through a wet etching process such as phosphoric acid stripping. Referring to FIG. 9E, in the same manner as shown in FIG. 3G of Embodiment 1, a selective epitaxial single crystalline film is partially grown on the sides of the active channel pattern 18 a to form source/drain extension layers 32 a.

[0123] In the same manner as shown in FIG. 3H of Embodiment 1, a conductive film such as doped polysilicon, metal, metal silicide, etc. is deposited on the surface of the resultant structure including the source/drain extension layers 32 a and then, etched back to form source/drain regions 34 a filling up the etched regions 30. Here, the epitaxial single crystalline film is thickly grown on the sides of the active channel pattern 18 a because it is grown only on the silicon region excluding the insulating layer patterns 60. Accordingly, a tail 34 a of the conductive film for source/drain may not remain under the sidewalls of the dummy gate pattern 26 in contrast to Embodiments 1 to 3.

[0124] Here, before depositing the conductive film, a tilted ion implantation may be executed to dope the source/drain extension layers 32 a comprised of the selective epitaxial single crystalline film with impurities. Alternatively or in addition, the source/drain extension layers 32 can be doped by solid-phase diffusing a dopant from the source/drain regions in a subsequent annealing process. In either case, the source/drain extension layers 32 a and the source/drain regions 34 a can have uniform doping profile in a direction perpendicular to the channel region.

[0125] Referring to FIG. 9F, in the same manner as shown in FIG. 3I of Embodiment 1, silicon nitride is deposited on the source/drain regions 34 a, the active channel pattern 18 a of the channel region and the substrate 10, thereby forming a mask layer. Then, the mask layer is planarized until the surface of the dummy gate pattern 26 is exposed, thereby forming a mask pattern 36 exposing the dummy gate pattern 26.

[0126] Referring to FIG. 9G, in the same manner as shown in FIG. 3K of Embodiment 1, the dummy gate pattern 26 is selectively removed by using the mask pattern 36, thereby forming a gate trench 38. Then, the etch-stopping layer pattern 24 exposed through the gate trench 38 is removed. If the active channel pattern 18 a of the channel region is not doped, an impurity is locally ion-implanted through the gate trench 38 to thereby dope the active channel pattern 18 a of the channel region. In some embodiments, the channel ion implantation is carried out such that the projected range is formed within each of the channel layers 16″. Alternatively, in other embodiments, the channel ion implantation is executed such that the channel layers 16″ have different doping concentrations from each other so that the obtained transistor successively operates according to the applied gate voltage.

[0127] Referring to FIG. 9H, in the same manner as shown in FIG. 3M of Embodiment 1, the field regions 22 are selectively etched using the source/drain regions 34 a as an etching mask, thereby exposing the sides of the active channel pattern 18 a of the channel region. Then, in the same manner as shown in FIG. 3N of Embodiment 1, the plurality of interchannel layer patterns 14 a″, 14 b″ and 14 c″ are selectively removed through an isotropic etching process, thereby forming a plurality of tunnels 42 and 42 b passing through the active channel pattern 18 a and a tunnel groove 42 c located at an uppermost position. Here, the second channel layer patterns 16 a″ and 16 b″ form a plurality of channels 44 a and 44 b.

[0128] Referring to FIG. 9I, in the same manner as shown in FIG. 3O of Embodiment 1, a thermal oxidation process is carried out to form a gate-insulating layer 46 on the surfaces of the plurality of channels 44 a and 44 b (particularly, including the plurality of tunnels 42 a and 42 b and the tunnel groove 42 c). Here, in order to reduce the surface roughness of the channels 44 a and 44 b, a heat treatment may be performed at a high temperature in a hydrogen (H₂) or argon (Ar) ambient before forming the gate-insulating layer 46.

[0129] Then, in the same manner as shown in FIG. 3P of Embodiment 1, a polysilicon gate electrode 48 is formed so as to extend through and/or fill up the tunnels 42 a and 42 b and the tunnel groove 42 c and to surround the plurality of channels 44 a and 44 b. A gate stack layer 50 comprising of metal silicide for reducing a gate resistance is formed on the top of the polysilicon gate electrode 48.

[0130] Referring to FIG. 9J, in the same manner as shown in FIG. 3R of Embodiment 1, the mask patterns 36 are removed and then, subsequent processes such as metal interconnection are carried out to complete the vertical MOS transistor.

[0131] According to the fourth embodiments of the present invention, the insulating layer patterns 60 are formed on the bottoms of the source/drain regions to thereby decrease the source/drain junction capacitance.

Embodiment 5

[0132]FIG. 10 is a cross-sectional view of a device in accordance with fifth embodiments of the present invention. In the present embodiments, the same elements as those in Embodiment 1 are indicated by the same numerals.

[0133] In the present embodiments, after performing processes in the same manner as shown in FIGS. 3A to 3F of Embodiment 1, a pre-active pattern 18 is etched away to form etched regions 30 where the source/drain regions are to be formed and an active channel pattern 18 a. Then, the etched regions 30 are filled with a selective epitaxial single crystalline film to form source/drain regions 34. Next, in the same manner as shown in FIGS. 3I to 3R, subsequent processes are executed to form the semiconductor device.

[0134] Accordingly, the present embodiment is similar to Embodiment 1 except that the etched regions 30 are completely filled by an epitaxial method to form the source/drain regions 34 without forming additional source/drain extension layers.

[0135] In the present embodiment, gate spacers 54 comprising an insulating material may be formed between a gate electrode 48 and the source/drain regions 34 by combining a method as shown in Embodiment 2 or 3. Further, insulating layer patterns 60 may be formed on the bottoms of the source/drain regions 34 by combining a method as shown in Embodiment 4.

Embodiment 6

[0136]FIG. 11 is a cross-sectional view of a semiconductor device in accordance with sixth embodiments of the present invention. In the present embodiments, the same elements as those in Embodiment 1 are indicated by the same numerals.

[0137] The semiconductor device of the present embodiments is similar to Embodiment 5 in which a pre-active pattern 18 is etched away to form etched regions for source/drain and an active channel pattern 18 a in the same manner as shown in FIGS. 3A to 3F of Embodiment 1, except that the conductive film such as doped polysilicon, metal, metal silicide, etc., is deposited and then, etched back to form source/drain regions 34 on the etched regions 30 instead of filling the etched regions 30 with a selective epitaxial single crystalline film as shown in Embodiment 5.

[0138] In the present embodiments, it may be unnecessary to form additional source/drain extension layers in the same manner as in Embodiment 5. Further, a vertical MOS transistor having multiple channels can be obtained by combining a method as shown in Embodiment 2, Embodiment 3 or Embodiment 4 with Embodiment 6.

Embodiment 7

[0139]FIG. 12 is a cross-sectional view of a semiconductor device in accordance with seventh embodiments of the present invention. The semiconductor device of the present embodiment is similar to that of Embodiment 5 except that the number of channels 44 and the thickness of tunnels are different from those of the semiconductor device shown in Embodiment 5 by controlling the thickness and the repetitive number of the interchannel layers and the channel layers constituting the active pattern.

Embodiment 8

[0140]FIG. 13 is a cross-sectional view of a semiconductor device in accordance with eighth embodiments of the present invention. The semiconductor device of the present embodiments is formed on an oxide layer 70 of SOI substrate in the same manner as shown in Embodiment 5 or Embodiment 6.

[0141] Particularly, there is provided a vertical MOS transistor having an active channel pattern comprising a plurality of channels 44 a, 44 b and 44 c on the oxide layer 70 of SOI substrate with tunnels interposed between each of the channels, source/drain regions 34 formed so as to connect with the plurality of channels 44 a, 44 b and 44 c on both sides of the active channel pattern and a gate electrode 48 formed on the active channel pattern so as to extend through or fill up the tunnels and to surround the plurality of channels 44 a, 44 b and 44 c.

[0142] The vertical MOS transistor can be obtained by combining a method as shown in the other previous Embodiments. As is well known to those having skill in the art, the SOI substrate has a lower semiconductor substrate (not shown) and the buried oxide layer 70 formed on the substrate.

[0143] In the present embodiments, a plurality of interchannel layers comprising single crystalline Ge or single crystalline SiGe film and a plurality of channel layers comprising single crystalline Si film are stacked alternately with each other on the buried oxide layer 70. Then, the plurality of interchannel layers and the plurality of channel layers are patterned to form a pre-active pattern.

Embodiment 9

[0144]FIG. 14 is a cross-sectional view of a semiconductor device in accordance with ninth embodiments of the present invention. The semiconductor device of the present embodiments is similar to that shown in FIG. 5 of Embodiment 5 except that the thickness (t) of the lowest tunnel filled with a gate electrode 48 is formed thicker than the other tunnels so as to reduce or prevent the operation of the parasitic transistor of the lowest channel 44 a. The same numerals indicate the same elements.

[0145] Particularly, in the process illustrated by referring to FIG. 3B in Embodiment 1, the thickness (t) of the lowest interchannel layer 14 a is formed thicker than the other interchannel layers 14 b and 14 c when a plurality of interchannel layers 14 and a plurality of channel layers 16 are stacked alternately with each other on a semiconductor substrate 10. In the same manner as shown in FIGS. 3D to 3F of Embodiment 1, the plurality of interchannel layers 14 and the plurality of channel layers 16 are patterned to form a pre-active pattern 18 and then, the pre-active pattern 19 is etched away until the surface of the substrate 10 is exposed, thereby defining regions where source/drain regions are to be formed and simultaneously, forming an active channel pattern 18 a including interchannel layer patterns and channel layer patterns.

[0146] In the same manner as in Embodiment 5, an epitaxial single crystalline film is grown so as to fill up the etched regions and then, doped up to the upper portion of the lower interchannel layer, thereby forming source/drain regions 34. Subsequent processes are similar to the above-described embodiments.

Embodiment 10

[0147]FIGS. 15A to 15E are cross-sectional views illustrating methods of manufacturing a semiconductor device in accordance with tenth embodiments of the present invention.

[0148] Referring to FIG. 15A, in the same manner as shown in FIGS. 3A to 3C of Embodiment 1, an pre-active pattern 18 in which a plurality of interchannel layers 14 and a plurality of channel layers 16 are stacked alternately with each other and field regions 22 surrounding the pre-active pattern 18 are formed on a substrate 10. In some embodiments, the plurality of interchannel layers 14 comprises single crystalline Ge or single crystalline SiGe film, while the plurality of channel layers 16 comprises single crystalline Si film.

[0149] Thereafter, in the same manner as shown in FIGS. 3D and 3E in Embodiment 1, a gate hard mask 29 including a dummy gate pattern (not shown) is formed on the pre-active pattern.

[0150] In the same manner as shown in FIG. 3F of Embodiment 1, the pre-active pattern 18 is etched away using the gate hard mask 29 until the surface of the substrate 10 is exposed, thereby forming regions 30 where source/drain are to be formed. As a result, only pre-active pattern 18 of the channel region remains.

[0151] Then, in the same manner as shown in FIG. 3G of Embodiment 1, a selective epitaxial single crystalline film is partially grown on the sides of the pre-active pattern 18 and the exposed surface of the substrate 10, thereby forming source/drain extension layers 32. A tilted ion implantation may be carried out to dope the source/drain extension layers 32 with impurities.

[0152] Next, as shown in FIG. 15A, silicon nitride is deposited on the entire surface of the resultant structure to form a first insulating layer 62. Particularly, the first insulating layer 62 comprised of an insulating material having an etch selectivity with respect to the pre-active pattern 18 and the field regions 22, e.g., silicon nitride, is formed on the entire surface of the substrate including the field regions 22 and the source/drain extension layers 32.

[0153] Referring to FIG. 15B, a second insulating layer 64 is deposited on the first insulating layer 62 so as to, in some embodiments, sufficiently fill up the regions where the source/drain are to be formed between the source/drain extension layers 32 and the field regions 22. The second insulating layer 64 comprises a material having an etch selectivity with respect to the first insulating layer 62. In some embodiments, the second insulating layer 64 is comprised of the same material as that constituting the field regions 62, e.g., silicon oxide.

[0154] Referring to FIG. 15C, the second insulating layer 64 is etched back to the lowest tunnel, thereby forming second insulating layer patterns 64 a on the bottoms of the regions where the source/drain are to be formed.

[0155] Referring to FIG. 15D, using the second insulating layer patterns 64 a as an etching mask, the first insulating layer 62 is etched back to form first insulating layer patterns 62 a under each of the second insulating layer patterns 64 a.

[0156] Referring to FIG. 15E, the regions where the source/drain are to be formed between the field regions 22 and the source/drain extension layers 32 are provided with or filled with a conductive film such as doped polysilicon, metal, metal silicide, etc., thereby forming source/drain regions 34.

[0157] Next, in the same manner as shown in FIGS. 3I to 3R of Embodiment 1, the semiconductor device is manufactured as shown in FIG. 15F.

[0158] According to the present embodiments, an insulating layer stack structure including the first insulating layer pattern 62 a and the second insulating layer pattern 64 a is formed on the bottoms of the source/drain regions 34, which can decrease in the source/drain junction capacitance.

Embodiment 11

[0159]FIGS. 16A to 16C are cross-sectional views illustrating semiconductor devices and methods of manufacturing the same in accordance with eleventh embodiments of the present invention. In the present embodiments, the same elements as those in Embodiments 1 to 10 are indicated by the same numerals.

[0160] Referring to FIG. 16A, for example, through a chemical vapor deposition method, an oxide layer 80 is formed on a semiconductor substrate 10 comprised of silicon (Si), silicon germanium (Si—Ge), silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI) and/or other conventional substrates/layers.

[0161] Referring to FIG. 16B, a photoresist film is coated on the oxide layer 80 and then, exposed and developed to form photoresist patterns 82 opening a region M where multiple channels will be formed.

[0162] Then, using the photoresist patterns 82 as a mask, the oxide layer 80 is dry-etched away to form oxide layer patterns 80 a defining a multiple channel region M and a single channel region S. That is, the oxide layer patterns 80 a remain only on the typical single channel regions S.

[0163] Subsequently, an impurity of the same conductivity as that of the substrate 10 is ion-implanted in the exposed substrate surface of the multiple channel region M, thereby forming heavily doped region 12 for reducing or preventing the operation of the bottom transistor.

[0164] Referring to FIG. 16C, the photoresist patterns 82 are removed by ashing and stripping processes. Then, through a selective epitaxial growth method, a plurality of interchannel layers 14 and a plurality of channel layers 16 are stacked alternately with each other on the regions excluding the oxide layer patterns 80 a, i.e., on the substrate surface of the multiple channel region M.

[0165] Particularly, a single crystalline Ge epitaxial film or a single crystalline Si—Ge epitaxial film is selectively grown to a thickness of about 300 Å on the surface of the substrate 10 excluding the oxide layer patterns 80 a, thereby forming a first interchannel layer 14 a. Then, a single crystalline Si epitaxial film having a thickness of about 300 Å is grown on the first interchannel layer 14 a to thereby form a first channel layer 16 a. Here, in order to previously perform the channel doping, the channel layer 16 may be formed of a doped single crystalline Si epitaxial film.

[0166] By doing so, no epitaxial film is grown on the single channel region S, while a pre-active pattern 18 in which the plurality of interchannel layers 14 and the plurality of channel layers 16 are stacked alternately each other is formed on the multiple channel region M.

[0167] Then, in the same manner as shown in Embodiments 1 to 10, subsequent processes are carried out to form the semiconductor device.

[0168] According to some embodiments of the present invention as described above, a plurality of thin channels is formed from one active pattern and the gate electrode is formed to surround the channels. Since the plurality of thin channels are stacked vertically, areas occupied by the channel region and the source/drain regions may be reduced as compared to the conventional fin-type MOS transistor.

[0169] Further, in some embodiments of the present invention, the source/drain regions are formed to have uniform doping profile in a direction perpendicular to the plurality of channels, so that uniform source/drain junction capacitance can be maintained even though the number and the area of the channels increase. Thus, while reducing or minimizing the junction capacitance, the current can increase to enhance the operating speed of the device.

[0170] According to some embodiments of the present invention, after alternately stacking the plurality of channel layers and the plurality of interchannel layers to form the active pattern, regions of the active pattern where source/drain regions are to be formed are etched away. In some embodiments, the etched regions are filled up with an epitaxial single crystalline film or a conductive material to form the source/drain regions. Since a horizontal length of the interchannel layer can be limited within a length region of the gate, the horizontal extension of the tunnels may be prevented when the interchannel layers are isotropically etched to form the tunnels in a subsequent process. So, a highly integrated MOS transistor having a gate length smaller than a channel width may be realized.

[0171] It will be understood that aspects of one or more embodiments of the present invention may be combined with each other to obtain a highly integrated vertical MOS transistor having the multiple channels.

[0172] In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. 

What is claimed is:
 1. An integrated circuit field effect transistor device comprising: a substrate having a surface; an active channel pattern on the surface comprising a plurality of channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel, a respective one of which is between respective adjacent ones of the channels; a gate electrode that surrounds the plurality of channels and that extends through the at least one tunnel; and a pair of source/drain regions, a respective one of which is on the surface at a respective one of opposite sides of the active channel pattern and is electrically connected to the plurality of channels.
 2. The device as claimed in claim 1 wherein the plurality of channels comprises first and second opposite sides and third and fourth opposite sides, wherein a respective one of the source/drain regions are located at a respective one of the first and second opposite sides and wherein the gate electrode surrounds the plurality of channels on the third and fourth opposite sides and extends through the at least one tunnel.
 3. The device as claimed in claim 1 wherein the plurality of channels comprises three channels that are stacked upon one another and are spaced part from one another to define two tunnels, a respective one of which is between respective adjacent ones of the three channels.
 4. The device as claimed in claim 1 wherein the plurality of channels and the plurality of tunnels extend parallel to the surface to define a series of alternating channels and tunnels that are stacked on the surface in a direction that is orthogonal to the surface.
 5. The device as claimed in claim 1 wherein the gate electrode fills the at least one tunnel.
 6. The device as claimed in claim 1, further comprising a gate-insulating layer between the gate electrode and the channels.
 7. The device as claimed in claim 1, wherein the channels comprise single crystalline silicon.
 8. The device as claimed in claim 1, wherein the gate electrode comprises polysilicon.
 9. The device as claimed in claim 8, further comprising a gate stack layer on the gate electrode opposite the substrate.
 10. The device as claimed in claim 9, wherein the gate stack layer comprises a metal silicide and/or an insulating material.
 11. The device as claimed in claim 8 wherein the gate electrode includes an outer surface remote from the substrate and a plurality of sidewalls that extend from the outer surface toward the substrate, and wherein the gate stack layer is comprised of a conductive material that is on the outer surface of the gate electrode and extends onto the sidewalls of the gate electrode.
 12. The device as claimed in claim 1, wherein the source/drain regions have uniform doping profile in a direction perpendicular to the surface.
 13. The device as claimed in claim 1, wherein the source/drain regions comprise single crystalline silicon.
 14. The device as claimed in claim 1, wherein the source/drain regions comprise polysilicon, metal and/or metal silicide.
 15. The device as claimed in claim 1, further comprising a pair of source/drain extension layers, a respective one of which is between a respective one of the source/drain regions and the channels.
 16. The device as claimed in claim 15, wherein the source/drain extension layers comprise single crystalline silicon, and the source/drain regions comprise polysilicon, metal and/or metal silicide.
 17. The device as claimed in claim 1, further comprising a heavily doped region in the substrate adjacent the active channel pattern.
 18. The device as claimed in claim 1, further comprising field regions that surround the source/drain regions and expose the active channel pattern.
 19. The device as claimed in claim 1, wherein the substrate comprises silicon, silicon germanium, silicon-on-insulator (SOI) and/or silicon germanium-on-insulator (SGOI).
 20. The device as claimed in claim 1, wherein at least one of the tunnels is narrower than at least one of the channels.
 21. The device as claimed in claim 20, further comprising gate spacers on opposite sidewalls of the tunnels, the gate spacers having a thickness corresponding to half a difference between a channel length and a tunnel length.
 22. The device as claimed in claim 1, further comprising an insulating layer between the source/drain regions and the surface of the substrate.
 23. The device as claimed in claim 22, wherein the insulating layer comprises a single film.
 24. The device as claimed in claim 22, wherein the insulating layer comprises a first insulating layer and a second insulating layer on the first insulating layer, the second insulating layer comprising a material having an etch selectivity with respect to the first insulating layer.
 25. The device as claimed in claim 1, wherein a tunnel that is closest to the surface is thicker than remaining tunnels.
 26. The device as claimed in claim 25, wherein the source/drain regions comprise a single crystalline film that is doped to adjacent a channel that is closest to the surface.
 27. The device as claimed in claim 1, wherein a surface of a channel that is furthest from the substrate surface includes therein a groove and wherein the gate electrode extends in the groove.
 28. A method of manufacturing an integrated circuit field effect transistor comprising: forming a pre-active pattern on a surface of a substrate, the pre-active pattern comprising a series of interchannel layers and channel layers stacked alternately upon each other; forming source/drain regions on the substrate, at opposite ends of the pre-active pattern; selectively removing the plurality of interchannel layers to form a plurality of tunnels passing through the pre-active pattern, thereby defining an active channel pattern comprising the tunnels and a plurality of channels comprising the channel layers; and forming a gate electrode in the tunnels and surrounding the channels.
 29. The method as claimed in claim 28 wherein the forming source/drain regions comprises: etching spaced apart regions of the pre-active pattern; and forming source/drain regions in the etched regions.
 30. The method as claimed in claim 29: wherein the etching spaced apart regions of the pre-active pattern comprises etching spaced apart regions of the pre-active pattern to define first and second opposite sides of the pre-active pattern; wherein the forming source/drain regions comprises forming a respective one of the source/drain regions at a respective one of the first and second opposite sides; and wherein the selectively removing comprises selectively removing the plurality of interchannel layers to form a plurality of tunnels that pass through the pre-active pattern from third to fourth sides thereof; and wherein the forming a gate electrode comprises forming a gate electrode that extends through the tunnels and surrounds the plurality of channels on the third and fourth sides.
 31. The method as claimed in claim 28 wherein the forming a pre-active pattern comprises forming a pre-active pattern that comprises three channel layers and two interchannel layers, a respective one of which is between respective adjacent ones of the three channel layers.
 32. The method as claimed in claim 29 wherein the etching is performed until the substrate surface is exposed.
 33. The method as claimed in claim 28 wherein the forming a gate electrode comprises forming a gate electrode to fill up the tunnels and surround the channels.
 34. The method as claimed in claim 28, wherein the substrate comprises silicon, silicon germanium, silicon-on-insulator (SOI) and/or silicon germanium-on-insulator (SGOI).
 35. The method as claimed in claim 28, wherein the channel layer and the interchannel layer comprise single crystalline semiconductor films having an etch selectivity with respect to each other.
 36. The method as claimed in claim 35, wherein the channel layer comprises silicon (Si) and the interchannel layer comprises germanium (Ge) and/or silicon germanium (SiGe).
 37. The method as claimed in claim 28, wherein the forming a pre-active pattern comprises: forming a layer pattern on the substrate to define a multiple channel region; and performing selective epitaxial growth to stack the interchannel layers and the channel layers alternately on each other on the substrate surface in the multiple channel region.
 38. The method as claimed in claim 37, further comprising implanting ions into the substrate in the multiple channel region, prior to forming the interchannel layers and the channel layers.
 39. The method as claimed in claim 28, wherein the following is performed after forming the pre-active pattern: etching the substrate excluding the pre-active pattern to a predetermined depth to thereby form an isolation trench; and forming a field region in the isolation trench.
 40. The method as claimed in claim 39, further comprising selectively etching the field regions to expose sides of the pre-active pattern, prior to forming the tunnels and the channels.
 41. The method as claimed in claim 29, wherein the etching comprises: forming a dummy gate pattern defining a gate region on the pre-active pattern; and etching the pre-active pattern until the surface of the substrate is exposed, by using the dummy gate pattern as an etching mask.
 42. The method as claimed in claim 41, wherein the following is performed prior to the selectively removing: forming a mask layer on the source/drain regions, the substrate and the pre-active pattern; planarizing the mask layer until a surface of the dummy gate pattern is exposed, to thereby form a mask pattern exposing the dummy gate pattern; removing the dummy gate pattern to form a gate trench using the mask pattern; and exposing sides of the pre-active pattern using the mask pattern.
 43. The method as claimed in claim 42, further comprising removing source/drain tails remaining on sides of the dummy gate pattern, after forming the gate trench.
 44. The method as claimed in claim 43, wherein the source/drain tails remaining on the sides of the dummy gate pattern are removed via an oxidation process and/or a wet etching process.
 45. The method as claimed in claim 29, wherein the forming a pre-active pattern is preceded by implanting ions to form a doped portion of the substrate, and wherein the forming a pre-active pattern comprises forming a pre-active pattern on the doped portion of the substrate.
 46. The method as claimed in claim 45, wherein the spaced apart regions of the pre-active pattern are etched to below a projected range of the ion-implantation.
 47. The method as claimed in claim 29, wherein the source/drain regions are formed by filling the spaced apart portions with a selective epitaxial single crystalline film.
 48. The method as claimed in claim 29, wherein a conductive film is deposited on the etched regions and then, the conductive film is etched back to form the source/drain regions.
 49. The method as claimed in claim 28, wherein the source/drain regions are formed by: partially growing a selective epitaxial single crystalline film on opposite ends of the pre-active pattern; depositing a conductive film on the selective epitaxial single crystalline film; and etching back the conductive film to leave the conductive film only within the etched regions.
 50. The method as claimed in claim 49, further comprising performing a tilted ion implantation to uniformly dope the selective epitaxial single crystalline film with impurities, prior to depositing the conductive film.
 51. The method as claimed in claim 49, further comprising performing heat treatment on the epitaxial single crystalline film, before depositing the conductive film.
 52. The method as claimed in claim 49, wherein the selective epitaxial single crystalline film is continuously grown on the sides of the pre-active pattern and surfaces of the etched regions.
 53. The method as claimed in claim 29, further comprising forming insulating layer patterns on surfaces of the etched regions prior to the forming source/drain regions in the etched regions.
 54. The method as claimed in claim 53, wherein the forming insulating layer patterns comprises: forming an oxidation blocking layer on the substrate including the spaced apart etched regions of the pre-active pattern; etching the substrate to a predetermined depth by using the oxidation blocking layer as an etching mask, to thereby expose a surface of the etched regions; and performing an oxidation process to form the insulating layer patterns on the exposed surface of the etched regions.
 55. The method as claimed in claim 49, wherein the selective epitaxial single crystalline film is grown only on the sides of the pre-active pattern.
 56. The method as claimed in claim 53, wherein each of the insulating layer patterns comprises a first insulating layer pattern on the etched regions and a second insulating layer pattern on the first insulating layer pattern.
 57. The method as claimed in claim 28, further comprising performing a channel ion implantation on the pre-active pattern prior to the selectively removing the plurality of interchannel layers.
 58. The method as claimed in claim 57, wherein the channel ion implantation is performed such that each of the channel layers has a different doping concentration from each other.
 59. The method as claimed in claim 28, wherein the interchannel layers are selectively removed by an isotropic etching process.
 60. The method as claimed in claim 28, further comprising forming a gate stack layer on the gate electrode.
 61. The method as claimed in claim 60, wherein the gate stack layer comprises metal silicide and/or an insulating material.
 62. The method as claimed in claim 60, further comprising forming a mask pattern having a gate trench that exposes a surface of the pre-active pattern before the active channel pattern is formed; and forming a gate stack layer comprising a conductive material so as to fill up the gate trench after the gate electrode is formed.
 63. The method as claimed in claim 60, wherein the following is performed before forming the active channel pattern: forming a mask pattern having a gate trench that exposes a surface of the pre-active pattern; and forming insulating layer spacers on inner sides of the gate trench, and wherein the following is performed after forming the gate electrode: selectively removing the insulating layer spacers so as to expose a portion of sidewalls of the gate electrode; forming a gate stack layer comprising a conductive material so as to fill the gate trench, the gate stack layer covering a surface and side portions of the gate electrode; and removing the insulating layer spacers.
 64. The method as claimed in claim 28, further comprising forming a gate-insulating layer on a surface of the channels so as to surround the channels, prior to the forming a gate electrode.
 65. The method as claimed in claim 64, further comprising performing a heat treatment in hydrogen or argon ambient prior to forming the gate-insulating layer.
 66. The method as claimed in claim 28, further comprising forming gate spacers comprised of an insulating material on sidewalls of the tunnels.
 67. The method as claimed in claim 66, wherein the gate spacers are formed by: partially lateral-etching the interchannel layers to form undercut regions; forming an insulating layer in the undercut regions; and etching the insulating layer to form the gate spacers in the undercut regions.
 68. The method as claimed in claim 28, wherein the interchannel layers of the pre-active pattern are formed such that an interchannel layer closest to the surface is thicker than remaining interchannel layers. 